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HT46R12A A/D Type 8-Bit OTP MCU
Technical Document
* Tools Information * FAQs * Application Note - HA0004E HT48 & HT46 MCU UART Software Implementation Method - HA0005E Controlling the I^2C bus with the HT48 & HT46 MCU Series - HA0011E HT48 & HT46 Keyboard Scan Program - HA0013E HT48 & HT46 LCM Interface Design - HA0075E MCU Reset and Oscillator Circuits Application Note - HA0101E Using the HT46R12A in an Induction Cooker
Features
* Operating voltage: * Power-down and wake-up functions for reduced
fSYS= 4MHz: 2.2V~5.5V fSYS= 8MHz: 3.3V~5.5V
* 17 bidirectional I/O lines * Two 8-bit programmable timer/event counters with
power consumption
* Up to 0.5ms instruction cycle with 8MHz system
clock at VDD= 5V
* 8-level subroutine nesting * 4 channel 9-bit resolution A/D converter * Two comparators with interrupt function * Bit manipulation instruction * 14-bit table read instruction * 63 powerful instructions * Instructions executed in one or two machine cycles * Low voltage reset function * 24-pin SKDIP/SOP package types available
overflow interrupt and 7-stage prescaler
* Single 8-bit programmable pulse generator - PPG -
output channel with prescaler and 8-bit programmable timer counter, supporting both active low or active high output
* Integrated crystal and RC oscillator * Watchdog Timer * 204814 program memory * 888 data memory RAM * PFD for audio generation
General Description
The HT46R12A is an 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions, oscillator options, multi-channel A/D Converter, HALT and wake-up functions, provide the device with the versatility to meet the requirements of wide range of A/D application possibilities such as external analog sensor signal processing. With the inclusion of two comparators and a fully integrated programmable pulse generator, the device is particularly suitable for use in products such as induction cookers and other home appliance application areas.
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Block Diagram
P r e s c a le r U X TM R0 TM R1 U X fS
YS
In te rru p t C ir c u it S ta c k P ro g ra m C o u n te r
TM R0C TM R0 PFD0 TM R1C TM R1 PFD1 M
M
fS
YS
P ro g ra m ROM
IN T C
/4
In s tr u c tio n R e g is te r
WDT
MP M U X D a ta M e m o ry PPG 0C PPGT0 PPG
M U
fS X
YS
/4
W DT OSC
P r e s c a le r
fS
YS
In s tr u c tio n D ecoder ALU T im in g G e n e ra to r
MUX
STATUS
PC PCC
P o rt C
S h ifte r 4 -C h a n n e l A /D C o n v e rte r
PC PC PC PC PC
0 /C 1 /C 2 /C 3 /C 4 /C
0V 0V 0O 1O 1V
IN IN U U IN T
+ T
-
OSC2
OS RE VD VS S
S D
C1
ACC
PB H ALT E N /D IS PBC
P o rt B
P B 0 /A N 0 ~ P B 3 /A N 3
LVR
PPG PPG 0C PPG PA PAC P o rt A
PA PA PA PA PA
0~P 3 /P 4 /T 5,P 7 /T
A2 FD MR0 A6 MR1
Pin Assignment
P B 1 /A N 1 1 2 3 4 5 6 7 8 9 10 11 12 P B 0 /A N 0 P A 3 /P F D PA2 PA1 PA0 C 1 V IN + P C 4 /C 1 V IN P C 3 /C 1 O U T P C 2 /C 0 O U T VSS P C 1 /C 0 V IN + 24 23 22 21 20 19 18 17 16 15 14 13 P B 2 /A N 2 P B 3 /A N 3 P A 4 /T M R 0 PA5 PA6 P A 7 /T M R 1 OSC2 OSC1 VDD RES PPG P C 0 /C 0 V IN -
H T46R 12A 2 4 S K D IP -A /S O P -A
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Pin Description
Pin Name PA0~PA2 PA3/PFD PA4/TMR0 PA5, PA6 PA7/TMR1 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 I/O Options Pull-high Wake-up PA3 or PFD Description Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA7 are pin-shared with PFD, TMR0 and TMR1 respectively. Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor functions are disabled automatically. Bi-directional 5-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A configuration option determines if all pins on the the port have pull-high resistors. C0VIN-, C0VIN+ and C0OUT are pin-shared with PC0, PC1 and PC2. Once the comparator 0 is enabled, the internal PC2 port control register can be used as input only, the PC2 output function and the PC0/PC1/PC2 pull-high resistors will be disabled automatically, however PC0 and PC1 maintain their I/O function. Software instructions determine if the Comparator 0 function is enabled or not. C1VIN+ and C1VIN- are the Comparator 1 inputs, C1OUT and C1VIN- are pin-shared with PC3 and PC4. Once the Comparator 1 function is enabled, the internal PC3 port control register can be used as input only, the PC3 output function and the PC3/PC4 pull-high resistors will be disabled automatically, however PC4 maintains its I/O function. Software instructions determine if the Comparator 1 function is enabled or not. The PC1/C0VIN+ pin is also the external interrupt input pin. A falling edge on this pin will form an interrupt trigger source whether the pin is setup as a Comparator input or I/O pin. Programmable pulse generator output pin, the pin is floating when the power is first applied. The PPG0 output level can be selected to be either active low or active high, selected via configuration option. OSC1, OSC2 are connected to an RC network or a Crystal (determined by option) for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to monitor the system clock at 1/4 frequency. Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground.
I/O
I/O
Pull-high
PC0/C0VINPC1/C0VIN+ PC2/C0OUT PC3/C1OUT PC4/C1VINC1VIN+
I/O
Pull-high I/O or Comparator
PPG
O
3/4
OSC1 OSC2 RES VDD VSS
I O I 3/4 3/4
Crystal or RC 3/4 3/4 3/4
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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D.C. Characteristics
Test Conditions Symbol Parameter VDD VDD Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR0 and TMR1 Input High Voltage for I/O Ports, TMR0 and TMR1 Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O Port & PPG Pin Sink Current 5V IOH 3V I/O Port & PPG Pin Source Current 5V RPH VAD EAD IADC 3V Pull-high Resistance 5V A/D Input Voltage A/D Conversion Error Additional Power Consumption if A/D Converter is Used 3/4 3/4 3V 5V 3/4 3/4 3V 5V 3V 5V 5V 3V No load, system HALT 5V 3V No load, system HALT 5V 3/4 3/4 3/4 3/4 3/4 3V 3/4 3/4 3/4 3/4 3/4 VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD 3/4 3/4 3/4 3/4 3/4 Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz ADC off No load, fSYS=4MHz ADC off No load, fSYS=8MHz ADC off 2.2 3.3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 20 10 0 3/4 3/4 3/4 3/4 3/4 0.6 2 0.8 2.5 4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3 8 20 -4 -10 60 30 3/4 0.5 0.5 1.5 5.5 5.5 1.5 4 1.5 4 8 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 3/4 3/4 3/4 3/4 100 50 VDD 1 1 3 V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA kW kW V LSB mA mA Min. Typ. Max. Unit Ta=25C
IDD1
IDD2
IDD3
ISTB1
ISTB2
VIL1 VIH1 VIL2 VIH2 VLVR IOL
Note:
If the comparator input voltage is not equal to VDD or VSS, there may be more IDD/ISTB current consumed by the pin-shared logic input function whether the comparator is enabled or disabled. Typically, the current for each comparator input pin is about 500mA (VDD=5V) if its input voltage is 2.5V.
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A.C. Characteristics
Test Conditions Symbol Parameter VDD fSYS System Clock Timer I/P Frequency (TMR0/TMR1) Watchdog Oscillator Period 5V tRES tSST tINT tAD tADC tADCS External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V 3/4 3/4 3/4 Power-up or Wake-up from HALT 3/4 3/4 3/4 3/4 400 400 0 0 45 32 1 3/4 1 1 3/4 3/4 3/4 3/4 3/4 3/4 90 65 3/4 1024 3/4 3/4 76 32 4000 8000 4000 8000 180 130 3/4 3/4 3/4 3/4 3/4 3/4 kHz kHz kHz kHz ms ms ms *tSYS ms ms tAD tAD Min. Typ. Max. Unit Ta=25C
fTIMER
tWDTOSC
Note: *tSYS=1/fSYS
Comparator Electrical Characteristics
Test Conditions Symbol Parameter VDD Comparator Operating Voltage Comparator Operating Current VOPOS1 VOPOS2 VCM tPD Note: Comparator Input Offset Voltage Comparator Input Offset Voltage Comparator Common Mode Voltage Range Comparator Response Time 3/4 5V 5V 5V 3/4 3/4 Conditions 3/4 3/4 3/4 By calibraton 3/4 With 10mV overdrive 2.2 3/4 -10 -2 VSS 3/4 3/4 3/4 3/4 3/4 3/4 3/4 5.5 200 10 2 VDD1.4V 2 Min. Typ. Max.
Ta=25C Unit V mA mV mV V ms
If the comparator input voltage is not equal to VDD or VSS, there may be more IDD/ISTB current consumed by the pin-shared logic input function whether the comparator is enabled or disabled. Typically, the current for each comparator input pin is about 500mA (VDD=5V) if its input voltage is 2.5V.
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Functional Description
Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme allows each instruction to be effectively executed in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are inT1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
cremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manages the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
S y s te m
C lo c k
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *10 0 0 0 0 0 0 0 *10 #10 S10 *9 0 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 1 @4 #4 S4 *3 0 0 1 1 0 0 1 @3 #3 S3 *2 0 1 0 1 0 1 0 @2 #2 S2 *1 0 0 0 0 0 0 0 @1 #1 S1 *0 0 0 0 0 0 0 0 @0 #0 S0
Mode Initial Reset Comparator 0 Interrupt Comparator 1 Interrupt External interrupt (from PC1) Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2
Program Counter Note: *10~*0: Program counter bits #10~#0: Instruction code bits 6 S10~S0: Stack register bits @7~@0: PCL bits August 3, 2007
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Program Memory - ROM The program memory is used to store the executable program instructions. It also contains data, table, interrupt entries, and is organized into 204814 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H
receives a falling edge, and if the interrupt is enabled, and the stack is not full, the program will jump to this location and begin execution.
* Location 010H
Location 010H is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 014H
Location 000H is reserved for program initialization. After a chip reset, the program will jump to this location and begin execution.
* Location 004H
Location 004H is reserved for the Comparator 0 interrupt service program. If the Comparator 0 output pin is activated, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 008H
Location 014H is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 018H
Location 008H is reserved for the Comparator 1 interrupt service program. If the Comparator 1 output pin is activated, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Location 00CH
Location 018H is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program will jump to this location and begin execution.
* Table location
Location 00CH is reserved for the external interrupt, which is the PC1 pin, service program. If the PC1 pin
000H 004H 008H 00C H 010H 014H 018H D e v ic e In itia liz a tio n P r o g r a m C o m p a r a to r 0 In te r r u p t S u b r o u tin e C o m p a r a to r 1 In te r r u p t S u b r o u tin e E x te rn a l In te rru p t (fro m PC1)
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry
n00H nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
700H 7FFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its
Program Memory
Any location in the ROM space can be used as a look-up table. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2 bits are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the Interrupt Service Routine both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the Interrupt Service Routine and errors may occur. Therefore, using the table read instruction in the main routine and simultaneously in the Interrupt Service Routine should be avoided. However, if the table read instruction has to be applied in both the main routine and the interrupt Service Routine, the interrupt should be disabled prior to the table read instruction. It should not be re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the Table Location
Instruction TABRDC [m] TABRDL [m]
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table Location Note: *10~*0: Table location bits @7~@0: Table pointer bits 7 P10~P8: Current program counter bits
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operation. These areas may function as normal program memory depending upon requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer, SP, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, indicated by a return instruction, RET or RETI, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented, using RET or RETI, the interrupt will be serviced. This feature prevents a stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow will occur and the first entry will be lost as only the most recent 8 return addresses are stored. Data Memory - RAM The data memory has a capacity of 1158 bits, and is divided into two functional groups, namely the special function registers and the general purpose data memory (888 bits), most of which are readable/writeable, although some are read only. The unused space before address 28H is reserved for future expansion usage and reading these locations will obtain a result of 00H. The general purpose data memory, addressed from 28H to 7FH is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the memory pointer registers, MP0 and MP1.
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H ADRL ADRH ADCR ACSR G e n e ra l P u rp o s e D a ta M e m o ry (8 8 B y te s ) PPG 0C PPGT0 CM P0C CO M 1C IN T C 1 TM R1 TM R1C PA PAC PB PBC PC PCC S p e c ia l P u r p o s e D a ta M e m o ry TM R0 TM R0C STATUS IN T C 0 ACC PCL TBLP TBLH In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1
:U nused R e a d a s "0 0 "
7FH
RAM Mapping
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Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation on [00H] and [02H] accesses the Data Memory pointed to by the MP0 and MP1 registers respectively. Reading locations 00H or 02H indirectly returns the result 00H. Writing to it indirectly leads to no operation. The function of data movement between two indirect addressing registers is not supported. The memory pointer registers, MP0 and MP1, are both 7-bit registers used to access the RAM by combining the corresponding indirect addressing registers. The memory pointer registers, MP0 and MP1, are 7-bit registers. Bit 7 of MP0 and MP1 are undefined and if read will return the result 1. Any write operation to MP0 and MP1 will only transfer the lower 7 bits of data to MP0 and MP1. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations - ADD, ADC, SUB, SBC, DAA * Logic operations - AND, OR, XOR, CPL * Rotation - RL, RR, RLC, RRC * Increment and Decrement - INC, DEC * Branch decision - SZ, SNZ, SIZ, SDZ
Status Register - STATUS This 8-bit register contains the 0 flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The device provides two internal timer/event counter 0/1 interrupts, two comparator interrupt, and an A/D converter interrupt. The interrupt control register 0, INTC0, and interrupt control register 1, INTC1, contains the interrupt control bits to enable or disable the interrupt and to record the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be automatically cleared. This scheme may prevent any further Function
The ALU not only saves the results of data operations but also changes the status register. Bit No. 0 Label C
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register
1 2 3 4 5 6, 7
AC Z OV PDF TO 3/4
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interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kind of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. The Comparator 0 output interrupt is initialised by setting the Comparator 0 output interrupt request flag (C0F; bit 4 of INTC0), which is caused by a falling edge transition from the Comparator 0 output. After the interrupt is enabled, and the stack is not full, and the C0F bit is set, a subroutine call to location 04H occurs. The related interrupt request flag, C0F, is reset, and the EMI bit is cleared to disable further maskable interrupts. The Comparator 1 output interrupt is initialised by setting the Comparator 1 output Interrupt request flag (C1F; bit 5 of the INTC0), which is caused by a falling edge transition from the Comparator 1 output. After the interrupt is enabled, and the stack is not full, and the C1F bit is set, a subroutine call to location 08H occurs. The related interrupt request flag, C1F, is reset, and the EMI bit is cleared to disable further maskable interrupts. The external interrupt is triggered by a failing edge on PC1 and the related request flag, EIF, is also set. After the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call occurs. The interrupt request flag, EIF, is reset and the EMI bit is cleared to disable further interrupts. The internal Timer/Event Counter 0 interrupt is initialised by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 4 of the INTC1), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 010H will occur. The related interrupt request flag, T0F, will be reset and the EMI bit cleared to disable further interrupts. The internal Timer/Event Counter 1 is operated in the same manner. The Timer/Event Counter 1 related interrupt request flag is T1F (bit 5 of the INTC1) and its subroutine call location is 014H. The related interrupt request flag, T1F, will be reset and the EMI bit cleared to disable further interrupts. Function Controls the master (global) interrupt (1=enable; 0=disable) Controls the Comparator 0 interrupt (1=enable; 0=disable) Controls the Comparator 1 interrupt (1=enable; 0=disable) Control external interrupt (1=enabled, 0=disabled) Comparator 0 request flag (1=active; 0=inactive) Comparator 1 request flag (1=active; 0=inactive) External interrupt flag (1=active, 0=inactive) Unused bit, read as 0 INTC0 (0BH) Register Bit No. 0 1 2 3 4 5 6 7 Label ET0I ET1I EADI 3/4 T0F T1F ADF 3/4 Function Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable) Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable) Controls the A/D converter interrupt (1=enable; 0=disable) Unused bit, read as 0 Internal Timer/Event Counter 0 request flag (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) A/D converter request flag (1=active; 0=inactive) Unused bit, read as 0 INTC1 (1EH) Register Rev. 1.00 10 August 3, 2007
Bit No. 0 1 2 3 4 5 6 7
Label EMI EC0I EC1I EEI C0F C1F EIF 3/4
HT46R12A
The A/D converter interrupt is initialised by setting the A/D converter request flag (ADF; bit 6 of the INTC1), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 018H will occur. The related interrupt request flag, ADF, will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgements are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1, if the stack is not full. To return from the interrupt subroutine, a RET or RETI instruction may be executed. The RETI instruction will set the EMI bit to re-enable an interrupt service, but the RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source Comparator 0 output interrupt Comparator 1 output interrupt External Interrupt - from PC1 Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow A/D converter completed overflow Priority Vector 1 2 3 4 5 6 004H 008H 00CH 010H 014H 018H There are two types of system oscillator circuits within the microcontroller. These are an RC oscillator and a Crystal oscillator, the choice of which is determined via a configuration option. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and whose resistance should range from 24kW to 1MW. Pin OSC2 can be used to monitor the system frequency at 1/4 the system frequency or can be used to synchronize external circuitry. The RC oscillator provides the most cost effective means of oscillator implementation, however, the frequency of oscillation may vary with VDD, temperature and process variations. It is, therefore, not recommended for use in timing sensitive applications where an accurate oscillator frequency is desired. If a Crystal oscillator is used, a crystal connected between OSC1 and OSC2 is required. No other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to obtain a frequency reference, but two external capacitors connected between OSC1, OSC2 and ground are required, if the oscillating frequency is less than 1MHz. When the system enters the Power-down mode the system oscillator is stopped to conserve power. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode where the system clock is stopped, the WDT oscillator will continue to operate with a period of approximately 65ms at 5V. The WDT oscillator can be disabled using a configuration option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented using a dedicated internal RC oscillator (WDT oscillator) or by the instruction clock, which is the system clock divided by 4. The choice of which one is used is determined by a configuration option. This timer is designed to prevent a software malfunction or a sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a configuration option. If the Watchdog Timer is disabled, all instructions relating to the WDT result in no operation. The WDT clock source will be subsequently divided by either 213, 214 , 215 or 216, determined by a configuration option, to get the actual WDT time-out period. Using the internal WDT clock source, the minimum WDT time-out period is about 600ms. This time-out period may vary with temperature, VDD and process variations. By selecting appropriate WDT options, longer time-out periods can be implemented. If the WDT time-out is selected to be fS/216, then a maximum time-out period of about 4.7s can be achieved.
The EMI, EC0I, EC1I, EEI, ET0I, ET1I, and EADI bits are all used to control the enable/disable status of the interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags, C0F, C1F, EIF, T0F, T1F, ADF are set, they remain in the INTC1 or INTC0 register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged if the CALL operates within the interrupt subroutine. Oscillator Configuration
V OSC1
DD
OSC1
OSC2 C r y s ta l O s c illa to r
fS Y S /4 N M O S O p e n D r a in
OSC2 RC O s c illa to r
System Oscillator
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S y s te m C lo c k /4 M ask o p tio n s e le c t fs D iv id e r fs/2
8
W D T P r e s c a le r
W DT OSC
M a s k O p tio n W D T C le a r
T fs fs fs fs
im e - o u t R e s e t /2 1 6 /2 1 5 /2 1 4 /2 1 3
Watchdog Timer
If the WDT oscillator is disabled, the WDT clock may still be sourced from the instruction clock and operate in the same manner except that in the Power-down mode the WDT will stop counting and lose its protecting purpose. In this situation the device can only be restarted by external logic. If the device operates in a noisy environment, using the internal WDT oscillator is strongly recommended, since the Power-down mode will stop the system clock. The WDT overflow under normal operation will initialise a device reset and set the status bit TO. In the Power-down mode, the overflow will initialise a warm reset where only the program counter and stack pointer are reset to 0. To clear the WDT contents, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the options - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal 1), any execution of the CLR WDT instruction will clear the WDT. If the CLR WDT1 and CLR WDT2 option is selected (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT, otherwise, the WDT will reset the chip due to a time-out. Power Down Operation - HALT The Power-down mode is entered by the execution of a HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT
The system can leave the Power-down mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for the device reset can be determined. The PDF flag is cleared by a system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the program counter and the stack pointer, the other circuits will maintain their original status. A port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device, setup via configuration options. Awakening from an I/O port stimulus, the program will resume execution at the next instruction. If it is awakening from an interrupt, two sequences may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power-down mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 system clock periods to resume normal operation. In other words, a dummy period will be inserted after the wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the Power-down mode.
oscillator will keep running, if the WDT is enabled and if its clock is sourced from the internal WDT oscillator.
* The contents of the Data Memory and registers re-
main unchanged.
* The WDT will be cleared and will start counting again,
if the WDT clock is sourced from the internal WDT oscillator.
* All of the I/O ports maintain their original status. * The PDF flag is set and the TO flag is cleared.
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Reset There are three ways in which a reset can occur:
* RES pin reset during normal operation * RES pin reset during Power-down * WDT time-out reset during normal operation
The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler, Divider WDT Timer/Event Counter PPG Timer PPG output Input/Output Ports Stack Pointer
V
DD
000H Disable Cleared Clear. After master reset, WDT begins counting Off Off Floating Input mode Points to the top of the stack
V
The WDT time-out during a Power-down is different from other device reset conditions, since it can perform a warm reset that resets only the program counter and the SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
DD
0 .0 1 m F 100kW RES 0 .1 m F B a s ic Reset C ir c u it 10kW 0 .1 m F 100kW RES H i-n o is e Reset C ir c u it
Note: u means unchanged To guarantee that the system oscillator is started and stabilised, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the Power-down state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from a Power-down will enable the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out at normal mode or RES reset).
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit.
HALT W DT
RES
W a rm
R eset
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Timing Chart
Reset Configuration
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The registers states are summarised in the following table. Register MP0 MP1 ACC Program Counter TBLP TBLH STATUS INTC0 TMR0 TMR0C TMR1 TMR1C PA PAC PB PBC PC PCC INTC1 PPG0C PPGT0 CMP0C CMP1C ADRL ADRH ADCR ACSR Note: Reset (Power On) 1xxx xxxx 1xxx xxxx xxxx xxxx 000H xxxx xxxx xxxx xxxx --00 xxxx -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 ---- 1111 ---- 1111 ---1 1111 ---1 1111 -000 -000 0000 0000 xxxx xxxx -000 1000 -000 1000 x--- ---xxxx xxxx 0100 0000 ---- --00 * stands for warm reset u stands for unchanged x stands for unknown WDT Time-out RES Reset (Normal Operation) (Normal Operation) 1uuu uuuu 1uuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --1u uuuu -000 0000 xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1--1111 1111 1111 1111 ---- 1111 ---- 1111 ---1 1111 ---1 1111 -000 -000 0000 0000 xxxx xxxx -000 1000 -000 1000 x--- ---xxxx xxxx 0100 0000 ---- --00 1uuu uuuu 1uuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --uu uuuu -000 0000 uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1--1111 1111 1111 1111 ---- 1111 ---- 1111 ---1 1111 ---1 1111 -000 -000 0000 0000 uuuu uuuu -000 1000 -000 1000 x--- ---xxxx xxxx 0100 0000 ---- --00 RES Reset (HALT) 1uuu uuuu 1uuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --01 uuuu -000 0000 uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1--1111 1111 1111 1111 ---- 1111 ---- 1111 ---1 1111 ---1 1111 -000 -000 0000 0000 uuuu uuuu -000 1000 -000 1000 x--- ---xxxx xxxx 0100 0000 ---- --00 WDT Time-out (HALT)* 1uuu uuuu 1uuu uuuu uuuu uuuu 000H uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uu-u u--uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu ---u uuuu ---u uuuu -uuu -uuu uuuu uuuu uuuu uuuu -uuu uuuu -uuu uuuu u--- ---uuuu uuuu uuuu uuuu ---- --uu
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Timer/Event Counter Two timer/event counters are implemented in the microcontroller. Timer/Event Counter 0 contains an 8-bit programmable count-up counter whose clock may be sourced from an external source or an internal clock source. The internal clock source comes from fSYS. Timer/Event Counter 1 contains an 8-bit programmable count-up counter whose clock may come from an external source or an internal clock source. The internal clock source comes from fSYS/4. The external clock input allows external events to be counted, time intervals or pulse widths to be measure. Using the internal system clock, the timer/event counter is has only one reference time base. If the timer clock source is sourced externally then timer intervals can be measured time intervals or pulse widths measured. Using the internal clock allows the user to generate an accurate time base. There are two registers associated with Timer/Event Counter 0, TMR0 and TMR0C (0EH) and two registers for Timer/Event Counter 1, TMR1 and TMR1C. Writing values into the TMR0 or TMR1 registers places a start value into the respective Timer/Event Counter 0/1 preload register while reading TMR0 or TMR1 retrieves the contents of the respective Timer/Event Counter. The TMR0C and TMR1C registers are the Timer/Event Counter control registers, which define the operating mode, the counting enable or disable and define the active edge. The T0M0/T1M0 and T0M1/T1M1 bits in the control registers define the operation mode. The event count mode is used to count external events, which means that the clock source will be sourced from the timer external pins, TMR0 and TMR1. The timer mode functions as a normal timer with the clock source coming from the internally selected clock source. The pulse width measurement mode can be used to measure the duration of a high or low level signal on either TMR0 or TMR1, whose time reference is based on the internally selected clock source. In the event count or timer mode, the timer/event counter starts counting from the current contents in the timer/event counter register and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag, which is the T0F bit in the INTC0 register or the T1F bit in the INTC1 register. In the pulse width measurement mode with the values of the T0ON/T1ON and T0E/T1E bits equal to 1, after the respective Timer/Event counter has received a transient from low to high, or high to low dependent upon the value of the T0E/T1E bit, it will start counting until the respective logic level on the TMR0 or TMR1 pin returns to its original level and resets the T0ON/T1ON bit. The measured result remains in the timer/event counter even if the activated transient occurs again, as only a single 1-cycle measurement is made. Not until the T0ON/T1ON bit is once again set can further measurements be made. In this operational mode, the timer/event counter begins counting not according to the logic level but according to the transient edges. In the case of a counter overflow, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e.the event and timer modes. To enable the counting operation, the Timer ON bit, namely the T0ON bit of TMR0C or the T1ON of TMR1C, should be set to 1. In the pulse width measurement mode, the T0ON/T1ON is automatically cleared after the measurement cycle is completed. But in the other two modes, the T0ON/T1ON can only be reset by instructions. The overflow of the Timer/Event Counters is one of the wake-up sources. The Timer/Event Counters can also be use to drive a PFD (Programmable Frequency Divider) output on pin PA3, selected via configuration options. Only one PFD, (PFD0 or PFD1) can be used with PA3 selected via configuration options. No matter what the operation mode is, writing a 0 to ET0I or ET1I disables the related interrupt service. When the PFD function is selected, executing a SET [PA].3 instruction will enable the PFD output while executing a CLR [PA].3 instruction will disable the PFD output. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. However if the timer/event counter is already on, any data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter will continue normal operation until an overflow occurs. When the timer/event counter is read, the clock is blocked to avoid errors, and as this may results in a counting error, his should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR0/TMR1 registers first, before turning on the related timer/event counter, as the initial power on value of the TMR0/TMR1 registers are unknown. Due to the timer/event structure, the programmer should pay special attention when using instructions to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable results. After this procedure, the timer/event function can be operated normally. Bit0~bit2 of TMR0C can be used to define the pre-scaling stages for the internal clock sources for the timer/event counter. The overflow signal of the timer/event counter are used to generate the PFD signals.
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fS
YS
8 - s ta g e P r e s c a le r 8 -1 M U X T0PSC 2~T0PSC 0 (1 /1 ~ 1 /1 2 8 ) TM R0 T0E T0M 1 T0M 0 T0O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r (T M R 0 ) PFD0 O v e r flo w T o In te rru p t f IN
T
D a ta b u s T0M 1 T0M 0 8 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter 0
fS TM R1 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r (T M R 1 ) PFD1 O v e r flo w T o In te rru p t
YS
/4
D a ta b u s T1M 1 T1M 0 8 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r R e lo a d
Timer/Event Counter 1
PFD0 M U X PFD1
T Q
PFD
P A 3 D a ta C T R L PFD S o u r c e O p tio n
PFD Source Option
Bit No.
Label
Function Define the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable the timer counting (0=disable; 1=enable) Unused bit, read as 0 Define the operating mode (T0M1, T0M0) 01 = Event count mode (External clock) 10 = Timer mode (Internal clock) 11 = Pulse Width measurement mode (External clock) 00 = Unused TMR0C (0EH) Register
0 1 2
T0PSC0 T0PSC1 T0PSC2
3
T0E
4 5
T0ON 3/4
6 7
T0M0 T0M1
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Bit No. 0~2 Label 3/4 Unused bit, read as 0 Defines the TMR1 active edge of the timer/event counter: In Event Counter Mode (T1M1,T1M0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge Enable/disable timer counting (0= disable; 1= enable) Unused bit, read as 0 Define the operating mode (T1M1, T1M0) 01= Event count mode (External clock) 10= Timer mode (Internal clock) 11= Pulse Width measurement mode (External clock) 00= Unused TMR1C (11H) Register Function
3
T1E
4 5
T1ON 3/4 T1M0 T1M1
6 7
Programmable Pulse Generator - PPG This HT46R12A device contains a single 8-bit PPG output channel. The PPG has a programmable period of 256T, where T can be 1/fSYS, 2/fSYS, 4/fSYS, 8/fSYS, 16/fSYS, 32/fSYS, 64/fSYS, 128/fSYS for an output pulse width. The PPG detects the falling edge of a trigger input, and then outputs a single pulse. The falling edge trigger may be sourced from either comparators or from a software trigger bit, which can be selected by software. The PPG is capable of generating pulse widths ranging from 0.25ms to 8.192ms for a system frequency of 4MHz. An active low or active high output can be selected for the PPG via a configuration option. Writing 00H to the PPGT0 register yields a pulse width of 256T output.
* PPG0 functional description
The PPG0 module consists of PPG0 timers, a PPG Mode Control, and two comparators. The PPG0 timer consists of a prescaler, one 8-bit up-counter timer,
and an 8-bit preload data register. The programmable pulse generator starts counting from the current contents in the preload register and ends at FFH(R) 00H. Once an overflow occurs, the counter is reloaded from the PPG0 timer counter preload register, and generates a signal to stop the PPG timer. The software trigger bit, P0ST, will be cleared when a PPG timer overflow occurs. There are two registers related to the PPG0 output function, a control register, PPG0C, and a timer preload register, PPGT0. The control register, PPG0C, defines the PPG0 input control mode trigger source, the enable or disable of the comparators, defines the PPG0 timer prescaler rate which have value of fSYS/1, fSYS/2, fSYS/4, fSYS/8, fSYS/16, fSYS/32, fSYS/64, fSYS/128, enable or disable stopping the PPG0 timer using the C0VO triggered input, enable or disable the restarting of the PPG0 timer using the C1VO triggered input, and control the PPG0 software trigger bit to trigger the PPG0 timer On or Off. The PPGT0 register is the PPG0 preload register, whose contents determine the output pulse width.
* PPG0C control register
Bit No. PPG0C (20H) POR value
7 P0ST 0
6 P0RSEN 0
5 P0SPEN 0
4 P0PSC2 0
3 P0PSC1 0
2 P0PSC0 0
1 CMP1EN 0
0 CMP0EN 0
CMP0EN: Enables or disables Comparator 0 (0: disable, 1: enable) CMP1EN: Enables or disables Comparator 1 (0: disable, 1: enable) P0PSC2, P0PSC1, P0PSC0: These three bits select the PPG0 timer prescaler rate. P0SPEN: Enables or disables the stopping of the PPG0 timer using the C0VO trigger input (0: disable, 1: enable) P0RSEN: Enables or disables the restarting of the PPG0 timer using the C1VO trigger input. (0: disable, 1: enable) P0ST: PPG0 software trigger bit. (0: Stop PPG0, 1: Restart PPG0)
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C 1 IN T C 0 IN T P0ST D a ta b u s P r e lo a d R e g is te r P P G 0 T im e r O n /O ff P P G 0 T im e r P P G 0 T im e r O ff C le a r P r e s c a le r P 0 fs P r e s c a le r P0PSC2 P0PSC1 P0PSC0 CM P0EN CM P1EN P 0 L E V ( O p tio n ) P P G 0 O u tp u t PPG O v e r flo w R e lo a d
P C 1 /C 0 V IN + P C 0 /C 0 V IN -
+ -
C0VO
P C 2 /C 0 O U T PPG M ode C o n tro l C 1 V IN + + C 1 V IN P C 3 /C 1 O U T C1VO
fS
YS
M U
fP X
PG
R is in g o r F a llg in g S e le c tio n T r ig g e r E d g e C o n tr o l PPG S ta rt PPG A c tiv e ( S y n c M o d e )
S ta r t S Y N C O p tio n
PPG0 Block Diagram
The CMP0EN and CMP1EN bits are used as the comparator enable or disable bits. CMP0EN= 0 (comparator is disabled) (R) PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all GPIO pins CMP1EN= 0 (comparator is disabled) (R) PC3/C1OUT, PC4/C1VIN+ are all GPIO. CMP0EN= 1 (comparator is enabled) (R) PC2 will be automatically set to be an input only, the PC2 output function and the PC0/PC1/PC2 pull-high resistors are disabled automatically but PC0/PC1 will maintain their I/O function. Software instructions determine if Comparator 0 is enabled or not. CMP1EN= 1 (comparator is enabled) (R) PC3 will be automatically set to be an input only, the PC3 output function and the PC3/PC4 pull-high resistors will be disabled automatically but PC4 will maintain its I/O function. Software instructions determine if Comparator 1 is enabled or not. Any action causing PPG to stop such as a PPG timer overflow, a SW stop (P0ST=1 (R) 0) - will cause the following actions to occur: Stop and clear the PPG prescaler (prescaler means prescaling counter, not P0PSC[2:0] in PPG0C) The PPG timer will be reloaded P0ST will cleared PPGO will be inactive For a start delay 0.5 (1/fSYS), when the start SYNC with clock is selected, the PPG pulse output will be trgiggered by either the rising or falling edge of the next clock(fsys) edge. After the PPG starts, the PPG output becomes active and its prescaler begins to count as soon as first transition (falling or raising) of the system clock arrives. After the first trigger has completed, the following clock edge trigger type is decided by the first one. For example, once the PPG starts and if the next arriving clock transition is a falling edge, the PPG will be triggered by a falling edge until the PPG stops and vice versa.
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EX1: Since the first trigger type is a falling edge after the PPG starts, the PPG timer is triggered by a falling edge until the PPG stops. tS Y S
S y s te m C lo c k
S ta r t T r ig g e r PPG P u ls e
< 0 .5 tS PPG T im e r
YS
n
n+1
n+2
EX2: Since the first trigger type is a raising edge after the PPG starts, the PPG timer is triggered by a raising edge until the PPG stops.
tS S y s te m C lo c k
YS
S ta r t T r ig g e r PPG P u ls e
< 0 .5 tS PPG T im e r
YS
n
n+1
n+2
PPG0C: CMP1EN, CMP0EN comparator enable/disable bits CMP0EN 0 1 Description Disable the Comparator 0. PC0/C0VIN-, PC1/C0VIN+, PC2/C0OUT are all I/O pins. Enable the Comparator 0. The PC0/C0VIN-, PC1/C0VIN+ are Comparator 0 input pins, PC2/C0OUT is a Comparator 0 output pin, PC2 output disabled, PC2 Pull-high resistor disabled. Description Disable the Comparator 1. PC3/C1OUT is a PGIO pin. Enable the Comparator 1. The PC3/C1OUT is a Comparator 1 output pin, PC3 output disable, PC3 Pull-high resistor disabled.
CMP1EN 0 1
Bits2~4 of the PPG0 control register, PPG0C, can be used to define the pre-scaling stages of the PPG0 timer counter clock. PPG0C: PPG0 timer prescaler rate bits P0PSC2 0 0 0 0 1 1 1 1 P0PSC1 0 0 1 1 0 0 1 1 P0PSC0 0 1 0 1 0 1 0 1 Prescaler Stage Definition P0fS=fSYS P0fS=fSYS/2 P0fS=fSYS/4 P0fS=fSYS/8 P0fS=fSYS/16 P0fS=fSYS/32 P0fS=fSYS/64 P0fS=fSYS/128
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P0SPEN is the PPG0 timer OFF enable or disable bit using the C0VO trigger input, if this bit is enabled, the PPG0 stop input can be triggered by C0VO or a PC2 falling edge. P0RSEN is the PPG0 restart enable or disable bit using the C1VO trigger input. If this bit is enabled, the PPG0 timer restart input can be trigger by C1VO or a PC3 falling edge.The status of C0VO or C1VO can be read by setting PC2 or PC3 to be an input pin when Comparator 0 or Comparator 1 is enabled. P0SPEN 0 Description Disable stopping the PPG0 timer using the C0VO trigger input. The PPG0 module output can be stopped by software control (P0ST) only. Enable stopping the PPG0 timer using the C0VO trigger input. The PPG0 module output can be stopped by a C0VO falling edge trigger or software control (P0ST bit is cleared to 0). Description Disable restarting the PPG0 timer using the C1VO trigger input. The PPG0 module output can be restarted by software control (P0ST) only. Enable restarting the PPG0 timer using the C1VO trigger input. The PPG0 module output can be restarted by a C1VO falling edge trigger or software control (P0ST is set to 1)
1
P0RSEN 0
1
The P0ST bit is a software trigger bit, if this bit is set to 1, the PPG0 timer will start counting and will be cleared when a PPG timer overflow occurs or PPG timer stop counting. If this bit is cleared to 0, the PPG0 timer will stop counting. When the PPG timer is counting and if a falling edge is generated from C1VO, PC3 or if the software control bit, P0ST, is set, the PPG0 timer counter will not be affected, therefore a re-trigger signal from C1V0, PC3 or P0ST will have no effect. The P0ST bit can also be used as a status bit for the PPG0 timer output. The PPG0 module output pulse active level is decided by a configuration option, if cleared to 0, the PPG output will be defined as an active high output, if the P0LEV bit is set to 1, the PPG output will be defined as an active low output. Another function, which enables the point when the PPG timer starts counting and if it is to be synchronised with the clock or not is determined by a configuration option. To start the PPG0 operation:
-
Set the PPG0 output active level - by configuration option. Select the input mode for PPG0 - P0RSEN, P0SPEN Determine the PPG0 output pulse width. Write data to PPGT0 and the PPG0 timer prescaler - P0PSC2, P0PSC1, PPSC0 Decide if the PPG0 timer start count is to be synchronised with the system clock (fSYS) or not via configuration option. When the PPG0 input is triggered by a C1VO falling edge transition or triggered by a software bit which is set to 1; (P0ST (R) 1), the PPG0 will start counting from the current contents of the preload register. When the PPG0 input is triggered by a C0VO falling edge transition, triggered by a software bit which is cleared to 0 (P0ST (R) 0) or when a PPG0 timer overflow occurs, the PPG0 will stop counting.
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Comparator The input voltage offset of the PPG comparator is adjustable by using common mode inputs to calibrate the offset.
Vr
CO S1 S2 CO S3
CN CP
The calibration steps are as follows:
* Set CnCOFM = 1 to offset the cancellation mode
- S3 is closed
* Set CnCRS to select which input pin is the reference voltage - S1 or S2 closed * Adjust CnCOF0~CnCOF3 until the output status changes * Set CnCOFM = 0 for the normal comparator operation mode.
Bit No. 0 1 2 3 4
Label C0COF0 C0COF1 C0COF2 C0COF3 C0CRS
Function
POR
Comparator input offset voltage cancellation control bits
1000B
Comparator input offset voltage cancellation reference selection bit 1/0: select CP/CN as the reference input Input offset voltage cancellation mode and comparator mode selection 1: input offset voltage cancellation mode 0: comparator mode Comparator output; positive logic Unused bit, read as 0 CMP0C (1BH) Register
0
5 6 7
C0COFM C0CMPOP 3/4
0 0 0
Bit No. 0 1 2 3 4
Label C1COF0 C1COF1 C1COF2 C1COF3 C1CRS
Function
POR
Comparator input offset voltage cancellation control bits
1000B
Comparator input offset voltage cancellation reference selection bit 1/0: select CP/CN as the reference input Input offset voltage cancellation mode and comparator mode selection 1: input offset voltage cancellation mode 0: comparator mode Comparator output; positive logic Unused bit, read as 0 CMP1C (1CH) Register
0
5 6 7
C1COFM C1CMPOP 3/4
0 0 0
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Input/Output Ports There are 16 bidirectional input/output lines in the microcontroller, labeled as PA, PB and PC, which are mapped to the data memory of [12H], [14H] and [16H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 16H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PCC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 17H. After a chip reset, these input/output lines remain at high levels or floating state (depending on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H, 14H or 16H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. Each I/O port has a pull-high option. Once the pull-high option is selected, the I/O port has a pull-high resistor, otherwise, theres none. Take note that a non-pull-high I/O port operating in input mode will cause a floating state. The PA3, PA4 and PA7 are pin-shared with PFD, TMR0 and TMR1 pins respectively. And the PC0, PC1, PC2, PC3 and PC4 are pin-shared with C0VIN1-, C0VIN+, C0OUT, C1OUT and C1VIN-. The PA3 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by a timer/event counter overflow signal. The input mode always remain in its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. Writing 1 to PA3 data register will enable the PFD output function and writing 0 will force the PA3 to remain at 0. The I/O functions of PA3 are shown below. I/O Mode PA3 Note: I/P O/P (Normal) (Normal) Logical Input Logical Output I/P (PFD) O/P (PFD)
Logical PFD Input (Timer on)
The PFD frequency is the timer/event counter overflow frequency divided by 2.
V
DD
C o n tr o l B it D a ta B u s D CK S C h ip R e s e t R e a d C o n tr o l R e g is te r Q W r ite C o n tr o l R e g is te r Q
P u ll- h ig h O p tio n PA PA PA PA PA PB PC PC PC PC PC M U X (P F D ) 0~P 3 /P 4 /T 5~P 7 /T 0 /A 0 /C 1 /C 2 /C 3 /C 4 /C A2 FD MR A6 MR N0 0V 0V 0O 1O 1V
0 1 ~P IN IN U U IN T T B 3 /A N 3 +
D a ta B it Q D CK S Q
W r ite D a ta R e g is te r
(P A 0 ) P A 3 (P P G 1 ) P F D M U X R e a d D a ta R e g is te r S y s te m W a k e - u p ( P A o n ly ) T M R 0 fo r P A 4 O n ly T M R 1 fo r P A 7 O n ly
EN
O P0~O P7
Input/Output Ports
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It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid consuming power under input floating state. The PFD (PFD0 or PFD1) output shares pin with PA3, as determined by options. When the PFD (PFD0 or PFD1) option is selected, setting PA3 1 (SET PA.3) will enable the PFD output and setting PA3 0 (CLR PA.3) will disable the PFD output and PA3 output at low level. The definitions of PFD control signal and PFD output frequency are listed in the following table. Timer PA3 Data PA3 Pad Timer Preload Register State Value OFF OFF ON ON Note: X X N N 0 1 0 1 0 U 0 PFD PFD Frequency X X X fTMR/[2(M-N)] Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D converter circuit is powered on. The EOCB bit (bit6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is completed. The START bit of the ADCR is used to begin the conversion of the A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In order to ensure that A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). Bit 7 of the ACSR register is used for test purposes only and must not be used for other purposes by the application program. Bit1 and bit0 of the ACSR register are used to select the A/D clock source. When the A/D conversion has completed, the A/D interrupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from 0 to 1. Important Note for A/D initialization: Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified, otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required. The A/D converter control register is used to control the A/D converter. The bit2~bit0 of the ADCR are used to select an analog input channel. Theres a total of 4 channels to select. The bit5~bit3 of the ADCR are used to set the PB configurations. PB can be an analog input or as digital I/O line determined by these 3 bits. PCR2 PCR1 PCR0 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x 3 PB3 PB3 PB3 PB3 AN3 2 PB2 PB2 PB2 AN2 AN2 1 PB1 PB1 AN1 AN1 AN1 0 PB0 AN0 AN0 AN0 AN0
Port B Configuration
X stands for unused U stands for unknown M is 256 for PFD N is preload value for the timer/event counter f T M R is input clock frequency for the timer/event counter
A/D Converter The 4 channels and 9-bit resolution A/D (8-bit accuracy) converter are implemented in this microcontroller. The reference voltage is VDD. The A/D converter contains four special registers which are; ADRL (24H), ADRH (25H), ADCR (26H) and ACSR (27H). The ADRH and ADRL are A/D result register higher-order byte and lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control register, which defines the A/D channel number, analog channel select, start A/D conversion control bit and end of A/D conversion flag. If users want to start an A/D conversion, define the PB configuration, select the converted analog channel, and give START bit a raising edge and falling edge (0(R)1(R)0). At the end of A/D conversion, the EOCB bit is cleared and an A/D converter interrupt occurs (if the A/D converter interrupt is enabled). The ACSR is A/D clock setting register, which is used to select the A/D clock source.
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Bit No. Label Selects the A/D converter clock source 00: system clock/2 ADCS0 01: system clock/8 ADCS1 10: system clock/32 11: undefined 3/4 TEST Unused bit, read as 0 For test mode used only ACSR (27H) Register Bit No. Label ACS2, ACS1, ACS0: Select A/D channel 0, 0, 0: AN0 0, 0, 1: AN1 0, 1, 0: AN2 0, 1, 1: AN3 1, x, x: Undefined, cannot be used Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is powered off to reduce power consumption Indicates end of A/D conversion. (0: end of A/D conversion) Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, otherwise the EOCB flag may have an undefined condition. See Important note for A/D initialization. Function Function
0 1
2~6 7
0 1 2
ACS0 ACS1 ACS2
3 4 5 6 7
PCR0 PCR1 PCR2 EOCB
START Starts the A/D conversion. (0(R)1(R)0= start; 0(R)1= Reset A/D converter and set EOCB to 1) ADCR (26H) Register
Register ADRL (24H) ADRH (25H) Note:
Bit7 D0 D8
Bit6 3/4 D7
Bit5 3/4 D6
Bit4 3/4 D5
Bit3 3/4 D4
Bit2 3/4 D3
Bit1 3/4 D2
Bit0 3/4 D1
D0~D8 is A/D conversion result data bit LSB~MSB. ADRL (24H), ADRH (25H) Register
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using EOCB Polling Method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : : ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRH ; read conversion result high byte value from the ADRH register mov adrh_buffer,a ; save result to user defined memory mov a,ADRL ; read conversion result low byte value from the ADRL register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next A/D conversion Rev. 1.00 24 August 3, 2007
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Example: using interrupt method to detect end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock mov mov a,00100000B ADCR,a : ; setup ADCR register to configure Port PB0~PB3 as A/D inputs ; and select AN0 to be connected to the A/D converter ; As the Port B channel bits have changed the following START ; signal (0-1-0) must be issued within 10 instruction cycles : Start_conversion: clr START set START clr START clr ADF set EADI set EMI : : : ; ADC interrupt service routine ADC_ISR: mov acc_stack,a mov a,STATUS mov status_stack,a : : mov a,ADRH mov adrh_buffer,a mov a,ADRL mov adrl_buffer,a clr START set START clr START : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a mov a,acc_stack reti
; reset A/D ; start A/D ; clear ADC interrupt request flag ; enable ADC interrupt ; enable global interrupt
; save ACC to user defined memory ; save STATUS to user defined memory ; read conversion result high byte value from the ADRH register ; save result to user defined register ; read conversion result low byte value from the ADRL register ; save result to user defined register ; reset A/D ; start A/D
; restore STATUS from user defined memory ; restore ACC from user defined memory
M in im u m START
o n e in s tr u c tio n c y c le n e e d e d , M a x im u m
te n in s tr u c tio n c y c le s a llo w e d
EOCB PC R2~ PCR0
A /D tA 000B
DCS
s a m p lin g tim e 100B
A /D tA
DCS
s a m p lin g tim e
A /D tA
DCS
s a m p lin g tim e 000B 1 . P B p o rt s e tu p a s I/O s 2 . A /D c o n v e r te r is p o w e r e d o ff to r e d u c e p o w e r c o n s u m p tio n
100B
101B
AC S2~ ACS0
000B P o w e r-o n R eset R e s e t A /D c o n v e rte r 1 : D e fin e P B c o n fig u r a tio n 2 : S e le c t a n a lo g c h a n n e l
010B S ta rt o f A /D c o n v e r s io n
000B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
001B S ta rt o f A /D c o n v e r s io n R e s e t A /D c o n v e rte r E n d o f A /D c o n v e r s io n
d o n 't c a r e
E n d o f A /D c o n v e r s io n tA D C c o n v e r s io n tim e
tA D C A /D c o n v e r s io n tim e N o te : A /D c lo c k m u s t b e fS tA D C S = 3 2 tA D tA D C = 7 6 tA D
YS
A /D
tA D C c o n v e r s io n tim e
A /D
/2 , fS
YS
/8 o r fS
YS
/3 2
A/D Conversion Timing
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Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) state has to be main-
The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
5 .5 V
V 3 .0 V 2 .2 V
LVR
tained for more than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function.
* The LVR uses the OR function with the external RES
0 .9 V
signal to perform a chip reset.
V 5 .5 V
DD
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
V
LVR
LVR
D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To ensure oscillator stabilisation, the SST provides an extra 1024 system clock pulse delay before normal operation commences. *2: Since the low voltage state has to be maintained for over 1ms, after this 1ms delay, the device will enter the reset mode.
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Options The following shows ten kinds of options in the microcontroller. ALL the options must be defined to ensure proper system function. Options OSC type selection. This option is to determine if an RC or crystal oscillator is chosen as system clock. WDT source selection. There are three types of selection: On-chip RC oscillator, instruction clock or disable the WDT. CLRWDT times selection. This option defines how to clear the WDT by instruction. One time means that the CLR WDT instruction can clear the WDT. Two times means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared. WDT time-out period selection. There are four types of selection: fS/213, fS/214, fS/215 and fS/216 Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT. Pull-high selection. This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports. PA0~PA7, can be independently selected. Pull-high selection. This option is to decide whether a pull-high resistance is viable or not in the input mode of the I/O ports. PB0~PB3, can be independently selected Pull-high selection. This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports. PC0~PC4, can be independently selected I/O pins share with other function selections. PA3/PFD: PA3 can be set as I/O pins or PFD output. PFD selection. If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as the PFD output. PFD0, PFD1 are generated by the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 respectively. Low voltage reset selection. Enable or disable LVR function. PPG0 output level selection; P0LEV. This option is to determine the PPG output level. Active Low or Active High selection. Disable this bit to 0, the PPG output will be defined as an active high output, Enable this bit to 1, the PPG output will be defined as an active low output PPG0 timer start counting synchronized with clock; P0TSYN. This option is to determine the PPG0 timer start counting is synchronized with input clock or not.
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Application Circuits
V
DD
PA0~PA2 VDD Reset C ir c u it RES 0 .1 m F VSS P A 3 /P F D P A 4 /T M R 0 100kW PA5~PA6 P A 7 /T M R 1 P B 0 /A N 0 P B 3 /A N 3 R P C 0 /C 0 V IN P C 1 /C 0 V IN + P C 2 /C 0 O U T P C 3 /C 1 O U T P C 4 /V 1 V IN HT46R12A C2 ~ V
DD
0 .1 m F
470pF
OSC
OSC1 fS
YS
R C S y s te m O s c illa to r 24kW /4
OSC2 OSC1 C r y s ta l/R e s o n a to r S y s te m O s c illa to r F o r R 1 , C 1 , C 2 s e e n o te
C1 R1
OSC C ir c u it
OSC1 OSC2
OSC2 OSC
C ir c u it
Note:
1. Crystal/resonator system oscillators For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. Reset circuit The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information.
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
(2)
(3) (1) (4)
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR [m] Description Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0 TO 0 PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
CLR WDT1 Description
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CLR WDT2 Description
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0* TO 0* PDF 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
CPL [m] Description Operation Affected flag(s)
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m] TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TO 3/4 DAA [m] Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
DECA [m] Description Operation Affected flag(s)
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4
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HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0 TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RETI Description Operation
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RL [m] Description Operation
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RLA [m] Description Operation
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RR [m] Description Operation
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRA [m] Description Operation
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
RRC [m] Description Operation
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Affected flag(s)
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RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SDZA [m] Description
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SIZA [m] Description
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
TABRDL [m] Description Operation
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
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Package Information
24-pin SKDIP (300mil) Outline Dimensions
A 24 B 1 13 12
H C D E F G
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 1235 255 125 125 16 50 3/4 295 345 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1265 265 135 145 20 70 3/4 315 360 15
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24-pin SOP (300mil) Outline Dimensions
24 A
13 B
1
12
C C' G H D E F
a
Symbol A B C C D E F G H a
Dimensions in mil Min. 394 290 14 590 92 3/4 4 32 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 614 104 3/4 3/4 38 12 10
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 24W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.5 24.8+0.3 -0.2 30.20.2
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Carrier Tape Dimensions
D
E F W C
P0
P1
t
B0
D1
P
K0 A0
SOP 24W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.1 11.50.1 1.55+0.1 1.5+0.25 4.00.1 2.00.1 10.90.1 15.90.1 3.10.1 0.350.05 21.3
Rev. 1.00
47
August 3, 2007
HT46R12A
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
48
August 3, 2007

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